Logic Compatible High-Performance Ferroelectric Transistor Memory

Silicon ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between gate stack and silicon channel suffers from high write voltage, limited endurance large read-after-write latency due to early IL breakdown charge trapping detrapping at the interface. We demonstrate low speed memory operation using an IL-free back-end-of-line (BEOL) compatible FeFET. fabricate FeFETs 28nm length 126nm width under a thermal budget <400C by integrating 5nm thick Hf0.5Zr0.5O2 amorphous Indium Tungsten Oxide (IWO) semiconductor channel. report 1.2V window read current of 10^5 for program erase, 20ns +/-2V pulses, <200ns, cycles exceeding 5x10^10 2-bit/cell programming capability. Array-level analysis establishes BEOL FeFET as promising candidate logic-compatible high-performance on-chip buffer multi-bit weight cell compute-in-memory accelerators.